december 5, 2000 3-1 eureka technology, inc. 4962 el camino real, suite 108 los altos, ca 94022 usa phone: +1 650-960-3800 fax: +1 650-960-3805 e-mail: info@eurekatech.com url: www.eurekatech.com features ? supports virtex?, virtex?-e, and spartan?-ii fpgas ? supports industry standard sdram and pc100 sdram dimm. ? supports register mode and non-register mode pc100 sdram dimm. ? programmable memory size and data width. ? supports industrial standard 16mbit, 64mbit, 128mbit and 256mbit sdrams. ? supports burst size of 1 to 8 and full page burst. ? supports zero wait state burst data transfer to maximize data bandwidth. ? programmable sdram access timing parameters. ? automatic refresh generation with programmable refresh intervals. ? optional error correction code (ecc). ? multiple external sdram partitions. ? supports external data buffer between user device and sdram data bus applications ? networking equipment ? communication equipment ? video systems ? image processing equipment ? medical equipment ? avionics ? pc peripherals alliancecore? facts core speci?cs supported family virtex device tested v50-6 clb slices 287 clock iobs 1 1 iobs 1 116 performance (mhz) 91 xilinx tools 3.2i special features none provided with core documentation user guide design file formats edif netlist constraints file top520.ucf verification vhdl or verilog test bench instantiation templates vhdl, verilog reference designs & application notes none additional items none simulation tool used model technology modelsim? 5.4b support support provided by eureka technology notes: 1. assuming all core i/os are routed off-chip EP520 sdram controller december 5, 2000 product specification
EP520 sdram controller 3-2 december 5, 2000 general description the EP520 sdram controller interfaces between a pro- cessor or dma device with an sdram. it performs sdram read and write access based on processor or dma requests. sdram timing such as row and column latency, precharge timing, and row access length are automatically handled by the sdram controller. all these timing parameters are set by the sdram controller on system reset and can be pro- grammed by the user during run time to optimize system performance. the EP520 supports all industry standard sdram organi- zations, ranging from 16mbit to 256mbit devices, and from x4 data width to x16 data width. the user can use multiple sdrams to build access word size from16-bit to 64-bit wide, or use standard sdram dimms to build the memory system. the sdram size and word size are programmable by the memory controller. zero wait state data bursting is supported by the sdram controller to maximize data throughput. the back-end inter- face to user device such as cpu or dma controller is a standard microprocessor bus with wait state control. it can be optimized easily to meet different application require- ments. functional description the EP520 core is partitioned into modules as shown in figure 1 and described below state machine based on the request signals ads_b and ce_b, the state machine sends control signals to the counters, address mux, and sdram control blocks to access to sdram. ready_b is asserted for each read data that is returned from the sdrams, or for each data that is written to the sdrams. if an access to the control registers block is requested on the cr_ads_b input, the state machine sends appropriate control signals to the control registers block to perform a register write. sdram control the sdram control block generates the cs_b, cas_b, ras_b and we_b signals and drives the appropriate address and dqm[7:0] at the proper timing. counters under the control of the state machine, the counters keep track of the burst length and various sdram timing param- eters, such as ras_b-to-cas_b delay, active command- to-precharge time, etc, so that every command is issued at the correct timing. these timing parameters are program- mable through the control registers. figure 1: EP520 sdram controller block diagram
december 5, 2000 3-3 eureka technology, inc. address mux the address mux takes the input address on addr[31:0] and drives the correct bank address on ba and row or col- umn address on maddr. control registers the user can program the sdram controller to support dif- ferent sdram sizes, burst lengths, and sdram timing parameters. the registers are accessed through the control register access signals, cr_xx (all cr_ signals). core modi?cations the sdram controller is designed in the xcv50pq240 device. cores for other packages can also be supported. eureka technology will contract to modify the core to your speci?cations. pinout the pinout of the EP520 core has not been ?xed to speci?c fpga i/o, thereby allowing ?exibility with a users applica- tion. signal names are shown in figure 1 and described in table 2. veri?cation methods functional simulation has been done using model technol- ogy modelsimtm 5.4b. static timing analysis has been done for all paths using the timing analyzer in xilinx foun- dation series 2.1i.recommended design experience the user must be familiar with hdl design methodology as well as instantiation of xilinx netlists in a hierarchical design environment. recommended design experience users should have a basic knowledge about sdram and decide the target device. ordering information if you have inquiries or want to license our core, please contact eureka technology directly. eureka technology retains the right to make changes to these speci?cations at any time without notice. phone : (650)960 3800 email : info@eurekatech.com related information xilinx programmable logic for information on xilinx programmable logic or develop- ment system software, contact your local xilinx sales of?ce, or: xilinx, inc. 2100 logic drive san jose, ca 95124 phone: +1 408-559-7778 fax: +1 408-559-7114 url: www.xilinx.com for general xilinx literature, contact: phone: 408-231-3386 (inside the usa) 408-879-5017 (outside the usa) email: literature@xilinx.com table 1: core signal pinout signal signal direction description addr[31:0] input address input ads_b input address strobe be_b[7:0] input byte enable blast_b input burst last ce_b input chip enable clk input system clock cr_adr[1:0] input register address cr_ads_b input control register access cr_dt[31:0] input register data cr_rdy_b output control register ready cr_wr input register write oe_b output output enable ofr_b output out of range ready_b output ready reset_b input system reset t_r_b output transmit/receive wr input write enable ba[1:0] output bank address cas_b output column address select cs_b[3:0] output chip select dqm[7:0] output data mask maddr[12:0] output memory address ras_b output row address select rege output register mode select we_b output write enable
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